Reduced-Precision Redundancy on FPGAs
Author:
Affiliation:
1. NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT 84602, USA
Abstract
Funder
National Science Foundation
Publisher
Hindawi Limited
Subject
Hardware and Architecture
Link
http://downloads.hindawi.com/journals/ijrc/2011/897189.pdf
Reference10 articles.
1. FPGA in the software radio
2. Space-Based FPGA Radio Receiver Design, Debug, and Development of a Radiation-Tolerant Computing System
3. Reconfigurable-system-on-chip implementation of data processing units for space applications
4. Characterization of soft errors caused by single event upsets in CMOS processes
5. Basic mechanisms and modeling of single-event upset in digital microelectronics
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