Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits-Reference-Cited by-同舟云学术

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Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits

Published:2023 Issue: Volume:11 Page:70691-70697
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Kim Seyoung¹^ORCID,Yang Seungho²^ORCID,Lim Hyein²,Lee Hyein²,Jeon Jongwook³^ORCID,Choi Jung Yun²,Kim Jaeha¹^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea

2. Memory Business Division, Samsung Electronics, Hwaseong, South Korea

3. Department of Electrical and Electronics Engineering, Konkuk University, Seoul, South Korea

Funder

National Research Foundation of Korea (NRF) Grant funded by the Korean Government [Ministry of Science and ICT (MSIT)]

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/6287639/10005208/10173498.pdf?arnumber=10173498

Reference35 articles.

1. Layout-Dependent Effects-Aware Analytical Analog Placement

2. EA-Based LDE-Aware Fast Analog Layout Retargeting With Device Abstraction

3. Modeling of layout-dependent stress effect in CMOS design

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