A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs-Reference-Cited by-同舟云学术

A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs

Published:2023 Issue: Volume:11 Page:36073-36081
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Habib Abdelrahman¹^ORCID,Dessouky Mohamed¹^ORCID,Naguib Ahmed²

Affiliation:

1. Electronics and Electrical Communications Engineering Department, Faculty of Engineering, Ain Shams University, Cairo, Egypt

2. Electronic Engineering Department, Military Technical College, Cairo, Egypt

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/6287639/10005208/10097748.pdf?arnumber=10097748

Reference13 articles.

1. A Calibration Technique for Bang-Bang ADPLLs Using Jitter Distribution Monitoring

2. A Multi-Bit PFD Architecture for ADPLLs with Built-In Jitter Self-Calibration

3. Jitter Minimization in Digital PLLs with Mid-Rise TDCs

4. A 76 fs rms jitter and ?40 dBc integrated-phase-noise 28-to-31 GHz frequency synthesizer based on digital sub-sampling PLL using optimally spaced voltage comparators and background loop-gain optimization;kim;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2019

5. The Role of PLLs in Future Wireline Transmitters

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