Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform
Author:
Affiliation:
1. Department of Computer Science and Engineering, University of California at San Diego, La Jolla, CA, USA
2. Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USA
Funder
NSF
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering
Link
https://ieeexplore.ieee.org/ielam/6287639/9668973/9798831-aam.pdf
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4. DTCO exploration for efficient standard cell power rails;chava;Proc SPIE,2018
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1. Invited Paper: The Scope and Challenges of Scaling in Advanced Technologies;Proceedings of the 2023 ACM International Workshop on System-Level Interconnect Pathfinding;2023-11-02
2. Gear-Ratio-Aware Standard Cell Layout Framework for DTCO Exploration;Proceedings of the 2023 ACM International Workshop on System-Level Interconnect Pathfinding;2023-11-02
3. Demonstration of Germanium Vertical Gate-All-Around Field-Effect Transistors Featured by Self-Aligned High-κ Metal Gates with Record High Performance;ACS Nano;2023-10-12
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