Worst-Case Communication Time Analysis for On-Chip Networks With Finite Buffers
Author:
Affiliation:
1. Laboratory of Embedded and Distributed Systems, University of Vale do Itajaí, Itajaí, Brazil
2. COPELABS—Lusófona University of Humanities and Technologies, Lisbon, Portugal
Funder
National Funds through the Funda??o para a Ci?ncia e a Tecnologia, I.P.
Conselho Nacional de Desenvolvimento Cient?fico e Tecnol?gico
Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/6287639/10005208/10065469.pdf?arnumber=10065469
Reference26 articles.
1. Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
2. Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching
3. Schedulability Analysis for Real Time On-Chip Communication with Wormhole Switching
4. Fixed priority scheduling of periodic task sets with arbitrary deadlines
5. Enhanced Schedulability via Minimal Routing with Mapping and Priority Assignment for Real-Time Network-on-chip
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