Schedulability Analysis for Real Time On-Chip Communication with Wormhole Switching

Author:

Shi Zheng1,Burns Alan1,Indrusiak Leandro Soares1

Affiliation:

1. University of York, UK

Abstract

In this paper, the authors discuss a real-time on-chip communication service with a priority-based wormhole switching policy. The authors present a novel off-line schedulability analysis approach, worst case network latency analysis. By evaluating diverse inter-relationships and service attributes among the traffic flows, this approach can predict the packet network latency for all practical situations. The simulation results provide evidence that communication latency calculated using the real time analysis approach is safe, closely matching the figures obtained from simulation.

Publisher

IGI Global

Subject

General Computer Science

Cited by 26 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Worst-Case Communication Time Analysis for On-Chip Networks With Finite Buffers;IEEE Access;2023

2. Design-Time Scheduling of Periodic, Hard Real-Time Flows for NoC-based Systems;2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2022-10-24

3. Design-Time Analysis of Real-Time Traffic for Networks-on-Chip using Constraint Models;2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2022-08-22

4. Precedence-Aware Automated Competitive Analysis of Real-Time Scheduling;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2020-11

5. Graph-Based Approach for Buffer-Aware Timing Analysis of Heterogeneous Wormhole NoCs Under Bursty Traffic;IEEE Access;2020

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