High-Throughput Low Power Area Efficient 17-bit 2’s Complement Multilayer Perceptron Components and Architecture for on-Chip Machine Learning in Implantable Devices-Reference-Cited by-同舟云学术

High-Throughput Low Power Area Efficient 17-bit 2’s Complement Multilayer Perceptron Components and Architecture for on-Chip Machine Learning in Implantable Devices

Published:2022 Issue: Volume:10 Page:92516-92531
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

James Romaine Brian¹^ORCID,Martin Mario Pereira¹

Affiliation:

1. Department of Engineering, Universidad Loyola Andalucía, Dos Hermanas, Seville, Spain

Funder

Universidad Loyola Andalucía

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/6287639/9668973/09870814.pdf?arnumber=9870814

Reference54 articles.

1. A High Speed SoftMax VLSI Architecture Based on Basic-Split

2. Generic model implementation of deep neural network activation functions using GWO-optimized SCPWL model on FPGA

3. Design Space Exploration of Neural Network Activation Function Circuits

4. Energy-Efficient Time-Domain Vector-by-Matrix Multiplier for Neurocomputing and Beyond

5. Analog perceptron circuit with DAC-based multiplier

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Towards Flexible and Low-Power Wireless Smart Sensors: Reconfigurable Analog-to-Feature Conversion for Healthcare Applications;Sensors;2024-02-03

2. Enhancing Disease Detection Accuracy in Machine Learning Through Low-Power Multipliers;2023 International Conference on Sustainable Communication Networks and Application (ICSCNA);2023-11-15

3. Novel 32nm CMOS Ternary 3‘s Complement Generator;2023 IEEE Devices for Integrated Circuit (DevIC);2023-04-07