An Analog-Assisted Digital LDO With Dynamic-Biasing Asynchronous Comparator-Reference-Cited by-同舟云学术

An Analog-Assisted Digital LDO With Dynamic-Biasing Asynchronous Comparator

Published:2022 Issue: Volume:10 Page:56996-57002
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Woo Yuet Ho¹,Yang Jianxin²,Li Junwen¹,Guo Jianping³^ORCID,Zheng Yanqi²^ORCID,Leung Ka Nang¹^ORCID

Affiliation:

1. Department of Electronic Engineering, The Chinese University of Hong Kong, Hong Kong, China

2. School of Microelectronics, South China University of Technology, Guangzhou, China

3. School of Electronics and Information Technology, Sun Yat-sen University, Guangzhou, China

Funder

Research Grant Council of Hong Kong Special Administrative Region (SAR) Government under Project The Chinese University of Hong Kong

Direct Grant of CUHK

Natural Science Foundation of Guangdong Province

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/6287639/9668973/09784888.pdf?arnumber=9784888

Reference15 articles.

1. An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator

2. A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active Voltage Positioning Using a Beat-Frequency Quantizer

3. 25.3 A 65 nm edge-chasing quantizer-based digital LDO featuring 4.58 ps-FoM and side-channel-attack resistance;he;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2020

4. A Hybrid Low-Dropout Regulator With Load Regulation Correction

5. A 200-ps-Response-Time Output-Capacitorless Low-Dropout Regulator With Unity-Gain Bandwidth >100 MHz in 130-nm CMOS

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