Author:
Liang-Fang Chao ,Hsing-Mean Sha E.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Computational Theory and Mathematics,Hardware and Architecture,Signal Processing
Cited by
55 articles.
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1. Efficient Pipelining of Synchronous Dataflow Graphs Via Graph Conversion;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-06
2. SARA: Scaling a Reconfigurable Dataflow Accelerator;2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA);2021-06
3. On the Design of Minimal-Cost Pipeline Systems Satisfying Hard/Soft Real-Time Constraints;IEEE Transactions on Emerging Topics in Computing;2021-01-01
4. Performance optimization for parallel systems with shared DWM via retiming, loop scheduling, and data placement;Journal of Systems Architecture;2021-01
5. Efficient Retiming of Unfolded Synchronous Dataflow Graphs;2019 24th International Conference on Engineering of Complex Computer Systems (ICECCS);2019-11