A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fsrms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector

Author:

Liang Yuan1ORCID,Boon Chirn Chye1ORCID

Affiliation:

1. School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore

Funder

Singapore Ministry of Education Academic Research Fund Tier 2

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Radiation

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 27.2–31.2 GHz 92-fs rms Integrated Jitter, Fractional-N Subsampling PLL Using Phase Rotating Technique in 65-nm CMOS;IEEE Transactions on Microwave Theory and Techniques;2023-12

2. A 25.8-GHz Integer-N CPPLL Achieving 60-fs rms Jitter and Robust Lock Acquisition Based on a Time–Amplifying Phase–Frequency Detector;IEEE Transactions on Microwave Theory and Techniques;2023-11

3. An Overview on the Low-Jitter Millimeter-Wave Frequency Synthesizer;2023 16th UK-Europe-China Workshop on Millimetre Waves and Terahertz Technologies (UCMMT);2023-08-31

4. Review of recent progress on solid‐state millimeter‐wave and terahertz signal sources;International Journal of Circuit Theory and Applications;2023-07-27

5. Design of fully differential fast SCL Schmitt-trigger delay element with tunable delay and hysteresis in design and run-time;Memories - Materials, Devices, Circuits and Systems;2023-07

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