A 22–33-GHz <i>G<sub>m</sub> </i>-Boosting Low-Power Noise-Canceling LNA in 40-nm CMOS Process-Reference-Cited by-同舟云学术

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A 22–33-GHz G_m -Boosting Low-Power Noise-Canceling LNA in 40-nm CMOS Process

Published:2024-07 Issue:7 Volume:72 Page:4017-4027
ISSN:0018-9480
Container-title:IEEE Transactions on Microwave Theory and Techniques
language:
Short-container-title:IEEE Trans. Microwave Theory Techn.

Author:

Khyalia Santosh Kumar¹^ORCID,Zele Rajesh H.¹,Chiong Chau-Ching²^ORCID,Wang Huei³^ORCID

Affiliation:

1. Department of Electrical Engineering, Indian Institute of Technology Bombay (IITB), Mumbai, India

2. Institute of Astronomy and Astrophysics, Academia Sinica, Taipei, Taiwan

3. Department of Electrical Engineering and the Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan

Funder

National Science and Technology Council (NSTC) of Republic of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/22/10581889/10406208.pdf?arnumber=10406208

Reference31 articles.

1. Design of Full Band UWB Common-Gate LNA

2. Design of Wideband LNAs Using Parallel-to-Series Resonant Matching Network Between Common-Gate and Common-Source Stages

3. A 28-GHz CMOS LNA with Stability-Enhanced Gm-Boosting Technique Using Transformers

4. A 24-43 GHz LNA with 3.1-3.7 dB Noise Figure and Embedded 3-Pole Elliptic High-Pass Response for 5G Applications in 22 nm FDSOI

5. A Wideband Variable Gain LNA With High OIP3 for 5G Using 40-nm Bulk CMOS

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