DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators

Author:

Bostanci F. Nisa1,Olgun Ataberk1,Orosa Lois2,Yaglikci A. Giray2,Kim Jeremie S.2,Hassan Hasan2,Ergin Oguz2,Mutlu Onur2

Affiliation:

1. TOBB University of Economics and Technology

2. ETH Zürich

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 10-Gb/s True Random Number Generator Using ML-Resistant Middle Square Method;IEEE Journal of Solid-State Circuits;2024-07

2. Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis;2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN);2024-06-24

3. FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration;ACM Transactions on Architecture and Code Optimization;2024-05-21

4. Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02

5. MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02

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