Encoder-Based Optimization of CNFET-Based Ternary Logic Circuits-Reference-Cited by-同舟云学术

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Encoder-Based Optimization of CNFET-Based Ternary Logic Circuits

Published:2018-03 Issue:2 Volume:17 Page:299-310
ISSN:1536-125X
Container-title:IEEE Transactions on Nanotechnology
language:
Short-container-title:IEEE Trans. Nanotechnology

Author:

Vudadha Chetan^ORCID,Rajagopalan Srinivasan^ORCID,Dusi Aditya^ORCID,Phaneendra P. Sai,Srinivas M. B.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

http://xplorestaging.ieee.org/ielx7/7729/8309492/08276321.pdf?arnumber=8276321

Cited by 17 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology;Physica Scripta;2024-05-09

2. Design of unbalanced 9:2 ternary encoder and 2:9 ternary decoder circuits in resistive random access memory and carbon nanotube field effect transistor technology;International Journal of Circuit Theory and Applications;2024-03-21

3. Ternary encoder and decoder designs in RRAM and CNTFET technologies;e-Prime - Advances in Electrical Engineering, Electronics and Energy;2024-03

4. Energy-Efficient High-Speed dynamic logic-based One-Trit multiplier in CNTFET technology;AEU - International Journal of Electronics and Communications;2024-02

5. Design and performance analysis of CNTFET based ternary encoders for next generation communication systems;AIP Conference Proceedings;2024

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