An Explicit Unified Drain Current Model for Silicon-Nanotube-Based Ultrathin Double Gate-All-Around <sc> mosfet</sc>s-Reference-Cited by-同舟云学术

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An Explicit Unified Drain Current Model for Silicon-Nanotube-Based Ultrathin Double Gate-All-Around mosfets

Published:2018-11 Issue:6 Volume:17 Page:1224-1234
ISSN:1536-125X
Container-title:IEEE Transactions on Nanotechnology
language:
Short-container-title:IEEE Trans. Nanotechnology

Author:

Kumar Arun^ORCID,Tiwari Pramod Kumar^ORCID

Funder

Defence Research and Development Organization, Ministry of Defence, Government of India

Council of Scientific and Industrial Research, Government of India

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

http://xplorestaging.ieee.org/ielx7/7729/8527562/08470250.pdf?arnumber=8470250

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A machine learning approach to accelerate reliability prediction in nanowire FETs from self-heating perspective;Microelectronics Reliability;2024-10

2. Modeling of inner-outer gates and temperature dependent gate-induced drain leakage current of junctionless double-gate-all-around FET;Microelectronics Journal;2024-04

3. Gate Stacked (GS) Junctionless Nanotube MOSFET: Design and Analysis;Silicon;2022-09-02

4. Temperature assessment of Si1-xGex source/drain heterojunction NT-JLFET for gate induced drain leakage ‒ A compact model;Superlattices and Microstructures;2021-08

5. Hafnium based high-k dielectric gate-stacked (GS) gate material engineered (GME) junctionless nanotube MOSFET for digital applications;Applied Physics A;2021-01

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