A machine learning approach to accelerate reliability prediction in nanowire FETs from self-heating perspective

Author:

Kumar T. Sandeep,Hazarika Anusha,Srinivas P.S.T.N.,Tiwari Pramod Kumar,Kumar Arun

Funder

Department of Science and Technology, Ministry of Science and Technology, India

Science and Engineering Research Board

Publisher

Elsevier BV

Reference31 articles.

1. 3nm G.A.A. technology featuring multi-bridge-channel FET for low power and high-performance applications;Bae,2018

2. A threshold voltage model of silicon-nanotube-based ultrathin double gate-all-around (DGAA) MOSFETs incorporating quantum confinement effects;Kumar;IEEE Trans. Nanotechnol.,2017

3. An explicit unified drain current model for silicon-nanotube-based ultrathin double gate-all-around mosfets;Kumar;IEEE Trans. Nanotechnol.,2018

4. Stacked-nanowire and FinFET transistors: guideline for the 7 nm node;Gaben,2015

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