An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic Multipliers-Reference-Cited by-同舟云学术

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An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic Multipliers

Published:2022-01-17 Issue: Volume: Page:
ISSN:
Container-title:2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)
language:
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Author:

Hou Lingxiao¹,Masuda Yutaka¹,Ishihara Tohru¹

Affiliation:

1. Graduate School of Informatics, Nagoya University,Nagoya,Japan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9712466/9712479/09712504.pdf?arnumber=9712504

Reference20 articles.

1. An efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition

2. An iterative logarithmic multiplier

3. A Hardware-Efficient Logarithmic Multiplier with Improved Accuracy

4. An area and delay efficient logarithmic mul tiplier;alla;Proceedings of the International Conference on Contemporary Computing and Applications (IC3A),0

5. A Two-Stage Operand Trimming Approximate Logarithmic Multiplier

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of Energy Efficient Logarithmic Approximate Multiplier;2023 5th International Conference on Circuits and Systems (ICCS);2023-10-27

2. An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2023-03-01

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