Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator-Reference-Cited by-同舟云学术

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Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator

Published:2022-01-17 Issue: Volume: Page:
ISSN:
Container-title:2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)
language:
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Author:

Fan Hongxiang¹,Ferianc Martin²,Que Zhiqiang¹,Li He³,Liu Shuanglong⁴,Niu Xinyu⁵,Luk Wayne¹

Affiliation:

1. School of Engineering, Imperial College,Dept. of Computing,London,UK

2. University College London,Dept. of Electronic and Electrical Engineering,UK

3. University of Cambridge,Dept. of Engineering,Cambridge,UK

4. Hunan Normal University,Changsha,China

5. Corerain Technologies Ltd.,Shenzhen,China

Funder

National Natural Science Foundation of China

Hunan Provincial Natural Science Foundation of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9712466/9712479/09712541.pdf?arnumber=9712541

Reference31 articles.

1. You Only Search Once: A Fast Automation Framework for Single-Stage DNN/Accelerator Co-design

2. Accuracy vs. Efficiency

3. Evolutionary cell aided design for neural network architectures;colangelo;ArXiv Preprint,2019

4. Hardware/Software Co-Exploration of Neural Architectures

5. Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Accelerator

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1. Quantization-Based Optimization Algorithm for Hardware Implementation of Convolution Neural Networks;Electronics;2024-04-30

2. Survey of convolutional neural network accelerators on field-programmable gate array platforms: architectures and optimization techniques;Journal of Real-Time Image Processing;2024-03-29

3. A Hardware Design Framework for Computer Vision Models Based on Reconfigurable Devices;ACM Transactions on Reconfigurable Technology and Systems;2024-01-15

4. A Memory Efficient Run-time Re-configurable Convolution IP Core for Deep Neural Networks Inference on FPGA Devices;2023 IEEE International Symposium on Smart Electronic Systems (iSES);2023-12-18

5. MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning Acceleration;2023 33rd International Conference on Field-Programmable Logic and Applications (FPL);2023-09-04

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