Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead

Author:

Karmokar Nibedita1,Madhusudan Meghna1,Sharma Arvind K.1,Harjani Ramesh1,Lin Mark Po-Hung2,Sapatnekar Sachin S.1

Affiliation:

1. University of Minnesota,USA

2. National Yang Ming Chiao Tung University,Taiwan

Publisher

IEEE

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Novel Automatic Placement Generation Tool for Current Mirror in Analog Circuits;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

2. Reinforcement Learning or Simulated Annealing for Analog Placement? A Study based on Bounded-Sliceline Grids;Proceedings of the 2024 International Symposium on Physical Design;2024-03-12

3. Reinforcing the Connection between Analog Design and EDA (Invited Paper);2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

4. GNN-Based Hierarchical Annotation for Analog Circuits;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-09

5. Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-09

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