Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs

Author:

Karmokar Nibedita1ORCID,Sharma Arvind K.1ORCID,Poojary Jitesh1ORCID,Madhusudan Meghna1,Harjani Ramesh1ORCID,Sapatnekar Sachin S.1ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, University of Minnesota Twin Cities, Minneapolis, MN, USA

Funder

Semiconductor Research Corporation

DARPA IDEA Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Reference26 articles.

1. CMOS

2. Linearity analysis on a series-split capacitor array for high-speed SAR ADCs;zhu;Proc 51st Midwest Symp Circuits Syst,2008

3. A 9.4-ENOB 1V 3.8¿W 100kS/s SAR ADC with Time-Domain Comparator

4. Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters

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