Modeling and design solutions to overcome warpage challenge for fan-out wafer level packaging (FO-WLP) technology

Author:

Che F.X.,Ho David,Ding Mian Zhi,Zhang Xiaowu

Publisher

IEEE

Cited by 27 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Investigation of Semiconductor Die Area as a Reference Variable for LCA;2024 Electronics Goes Green 2024+ (EGG);2024-06-18

2. Polymer-Based wafer-Level Warpage Prediction and Regulation for the Advanced Packaging;2024 IEEE 19th International Conference on Nano/Micro Engineered and Molecular Systems (NEMS);2024-05-02

3. Fan-Out Technology;Flip Chip, Hybrid Bonding, Fan-In, and Fan-Out Technology;2024

4. Fan-out Wafer-level Packaging Process Integration for Artificial Intelligence Real Dies;2023 18th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT);2023-10-25

5. Solution to Optimize Warpage performance for 2.5D Fanout Packaging;2023 24th International Conference on Electronic Packaging Technology (ICEPT);2023-08-08

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