Study of the die position accuracy in the fabrication process of a die first type FO-PLP

Author:

Nishido Keisuke,Onozeki Hitoshi,Suzuki Naoya,Nonaka Toshihisa

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Effects of Dielectric Curing Temperature on the Interfacial Reliability of Cu/Ti/PBO for FOWLP Applications;Electronic Materials Letters;2024-02-19

2. Study on the Application of Auger Electron Spectroscopy in RDL Failure Analysis;2023 24th International Conference on Electronic Packaging Technology (ICEPT);2023-08-08

3. Integration Strategy on Low-Cost Chip-First Fan-Out Panel Level Packaging;2022 China Semiconductor Technology International Conference (CSTIC);2022-06-20

4. "Molded-package-last" Process for Fan-out System in Package (FO-SiP);2020 IEEE 70th Electronic Components and Technology Conference (ECTC);2020-06

5. Expanding of Fan Out Wafer Level/Panel Level Package Technology and the Promising Future;Journal of The Japan Institute of Electronics Packaging;2019-08-01

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