Expanding of Fan Out Wafer Level/Panel Level Package Technology and the Promising Future
Author:
Affiliation:
1. Information and Communication Business Headquarters, Hitachi Chemical Co., Ltd.
Publisher
Japan Institute of Electronics Packaging
Subject
Electrical and Electronic Engineering
Link
https://www.jstage.jst.go.jp/article/jiep/22/5/22_380/_pdf
Reference15 articles.
1. 1) M. Brunnbauer, E. Fürgut, G. Beer, and T. Meyer: "Embedded wafer level ball grid array (eWLB)," 2006, 8th Electronics Packaging Technology Conference, pp. 1–5
2. 2) http://www.statschippac.com/~/media/Files/DocLibrary/whitepapers/2010/STATSChipPAC_EPTC2010_3D_eWLB_ST_E5_2_P0303.ashx
3. 3) C.-F. Tseng, C.-S. Liu, C.-H. Wu, and D. Yu: "InFO (Wafer Level Integrated Fan-Out) Technology," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), pp. 1–6
4. 4) http://www.samsungsem.com/global/support/regular/1479814_3584.jsp
5. 5) J. Vardaman: "Markets and Drivers for FO-WLP: How Far Will it Go?," 2017 SEMICON TAIWAN
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