Constraining LDPC degree distributions for improved error floor performance
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Science Applications,Modeling and Simulation
Link
http://xplorestaging.ieee.org/ielx5/4234/33437/01584380.pdf?arnumber=1584380
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Low Density Parity Check Codes;Channel Coding Techniques for Wireless Communications;2019
2. A new two‐stage decoding scheme with unreliable path search to lower the error‐floor for low‐density parity‐check codes;IET Communications;2017-09
3. Low Density Parity Check Codes;Channel Coding Techniques for Wireless Communications;2015
4. Shorten LDPC Codes with Better Performance;Applied Mechanics and Materials;2014-02
5. Multi-Stage Decoding Scheme with Post-Processing for LDPC Codes to Lower the Error Floors;IEICE Transactions on Communications;2011
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