Multi-Stage Decoding Scheme with Post-Processing for LDPC Codes to Lower the Error Floors-Reference-Cited by-同舟云学术

Multi-Stage Decoding Scheme with Post-Processing for LDPC Codes to Lower the Error Floors

Published:2011 Issue:8 Volume:E94-B Page:2375-2377
ISSN:0916-8516
Container-title:IEICE Transactions on Communications
language:en
Short-container-title:IEICE Trans. Commun.

Author:

SHIN Beomkyu¹,PARK Hosung¹,NO Jong-Seon¹,CHUNG Habong²

Affiliation:

1. Department of Electrical Engineering and Computer Science, INMC, Seoul National University

2. School of Electronics and Electrical Engineering, Hongik University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Software

Link

http://www.jstage.jst.go.jp/article/transcom/E94.B/8/E94.B_8_2375/_pdf

Reference10 articles.

1. [1] S.J. Johnson and S.R. Weller, “Constraining LDPC degree distributions for improved error floor performance,” IEEE Commun. Lett., vol.10, no.2, pp.103-105, Feb. 2006.

2. [2] Z. He, P. Fortier, and S. Roy, “A class of irregular LDPC codes with low error floor and low encoding complexity,” IEEE Commun. Lett., vol.10, no.5, pp.372-374, May 2006.

3. [3] T. Richardson, “Error floors of LDPC codes,” Proc. Allerton Conference on Communications, Control, and Computing, pp.1426-1435, Monticello, Oct. 2003.

4. [4] Y. Han and W.E. Ryan, “LDPC decoder strategies for achieving low error floors,” Proc. Information Theory and Applications Workshop, pp.277-286, Jan. 2008.

5. [5] S. Lander and O. Milenkovic, “Algorithmic and combinatorial analysis of trapping sets in structured LDPC codes,” Proc. Int. Conf. on Wireless Networks, Comm. and Mobile Computing, pp.630-635, June 2005.

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