A 10.7–14.1 GHz Reconfigurable Octacore DCO with −126 dBc/Hz Phase Noise at 1 MHz offset in 28 nm CMOS
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9489353/9490399/09490439.pdf?arnumber=9490439
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique;IEEE Journal of Solid-State Circuits;2024-08
2. A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique;IEEE Journal of Solid-State Circuits;2023-10
3. A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner;IEEE Journal of Solid-State Circuits;2023-03
4. A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS;IEEE Journal of Solid-State Circuits;2023-02
5. Ultra-Low Phase Noise X-Band BiCMOS VCOs Leveraging the Series Resonance;IEEE Journal of Solid-State Circuits;2022-12
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