A High-Performance, Energy-Efficient Modular DMA Engine Architecture-Reference-Cited by-同舟云学术

A High-Performance, Energy-Efficient Modular DMA Engine Architecture

Published:2024-01 Issue:1 Volume:73 Page:263-277
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Benz Thomas¹^ORCID,Rogenmoser Michael¹^ORCID,Scheffler Paul¹^ORCID,Riedel Samuel¹^ORCID,Ottaviano Alessandro¹^ORCID,Kurth Andreas¹^ORCID,Hoefler Torsten²^ORCID,Benini Luca³^ORCID

Affiliation:

1. Integrated Systems Laboratory (IIS), ETH Zurich, Zürich, Switzerland

2. Scalable Parallel Computing Laboratory (SPCL), ETH Zurich, Zürich, Switzerland

3. Integrated Systems Laboratory (IIS), ETH Zurich, Switzerland

Funder

European High Performance Computing Joint Undertaking

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx7/12/10372122/10311078.pdf?arnumber=10311078

Reference42 articles.

1. MT-DMA: A DMA Controller Supporting Efficient Matrix Transposition for Digital Signal Processing

2. NVIDIA A100 Tensor Core GPU: Performance and Innovation

3. Future Scaling of Memory Hierarchy for Tensor Cores and Eliminating Redundant Shared Memory Traffic Using Inter-Warp Multicasting

4. Xe HPC Ponte Vecchio

5. HAM: Hotspot-Aware Manager for Improving Communications With 3D-Stacked Memory

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