Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology-Reference-Cited by-同舟云学术

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Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology

Published:2018-08 Issue: Volume: Page:
ISSN:
Container-title:2018 21st Euromicro Conference on Digital System Design (DSD)
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Author:

Danger Jean-Luc,Yashiro Risa,Graba Tarik,Mathieu Yves,Si-Merabet Abdelmalek,Sakiyama Kazuo,Miura Noriyuki,Nagata Makoto

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8490807/8491778/08491861.pdf?arnumber=8491861

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Impact of Process Mismatch and Device Aging on SR-Latch Based True Random Number Generators;Lecture Notes in Computer Science;2024

2. Special Session: Security Verification & Testing for SR-Latch TRNGs;2023 IEEE 41st VLSI Test Symposium (VTS);2023-04-24

3. A Unified Multibit PUF and TRNG Based on Ring Oscillators for Secure IoT Devices;IEEE Internet of Things Journal;2023-04-01

4. Exploiting the DD-Cell as an Ultra-Compact Entropy Source for an FPGA-Based Re-Configurable PUF-TRNG Architecture;IEEE Access;2023

5. Research on Highly Portable Lightweight Physical Unclonable Functions Using Multiplexer Entropy Sources;J ELECTRON INF TECHN;2023

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