A Compact Model for Superconductor- Insulator-Superconductor (SIS) Josephson Junctions
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/55/9147077/09116823.pdf?arnumber=9116823
Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A new behavioral-level model of superconducting Josephson junctions with Simulink;Journal of Computational Electronics;2024-08-03
2. Wafer-scale CMOS-compatible graphene Josephson field-effect transistors;Applied Physics Letters;2024-07-01
3. Ultra-Area-Efficient Cryogenic XNOR Logic Gate with Superconducting Heater Cryotron to Advance High-Performance Computing;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12
4. Josephson Sampler Response Using a Binary Search Algorithm;IEEE Transactions on Applied Superconductivity;2024-05
5. Gate-controlled near-surface Josephson junctions;Applied Physics Letters;2024-01-22
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