Design of SHA-1 Algorithm Based on FPGA
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5479081/5480279/05480770.pdf?arnumber=5480770
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. RECO-ASCON: Reconfigurable ASCON hash functions for IoT applications;Integration;2023-11
2. Implementation of a 32-Bit RISC-V Processor with Cryptography Accelerators on FPGA and ASIC;2022 IEEE Ninth International Conference on Communications and Electronics (ICCE);2022-07-27
3. Performance Analysis of Secure Hash Algorithm-2 (SHA-) and Implementing on FPGA;ICT with Intelligent Applications;2021-12-06
4. Digitized data validation using dual color images with improved robustness and error correction facility;Sādhanā;2021-06-09
5. Securing CAN FD by implementing AES-128, SHA256, and Message Counter based on FPGA;2021 IEEE International Conference on Electro Information Technology (EIT);2021-05-14
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