Author:
Prasad Y Bhavani,Chokkakula Ganesh,Reddy P Srikanth,Samhitha N. R.
Cited by
4 articles.
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1. An Efficient High Performance GDI based 4-bit Vedic Multiplier in 32nm Technology;2023 Global Conference on Information Technologies and Communications (GCITC);2023-12-01
2. FPGA implementation of energy efficient Vedic multiplier using CSA architecture;2023 9th International Conference on Smart Structures and Systems (ICSSS);2023-11-23
3. High-Speed Vedic Multiplier Implementation Using Memristive and Speculative Adders;2022 International Conference on Computing, Communication and Power Technology (IC3P);2022-01
4. High Speed, Area and Power Efficient 32-bit Vedic Multipliers;Proceedings of the 7th International Conference on Computing Communication and Networking Technologies;2016-07-06