FPGA implementation of energy efficient Vedic multiplier using CSA architecture
Author:
Affiliation:
1. Chennai Institute of Technology,Center for System Design,Chennai,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10406300/10406306/10407086.pdf?arnumber=10407086
Reference20 articles.
1. Implementation of high speed vedic multiplier using modified adder
2. Design and Implementation of an Efficient Modified Vedic Multiplier Incorporating Fast Adder and Its Applications;Chaya;International Research Journal of Engineering and Technology (IRJET),2021
3. Performance Analysis of a 32-Bit Multiplier with a Carry-Look-Ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDL
4. Design and Implementation of 8-bit Vedic Multiplier;Pai;International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (An ISO 3297: 2007 Certified Organization),2013
5. Implementation of vedic multiplier using Kogge-stone adder
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