An Automated SerDes Frontend Generator Verified With a 16-nm Instance Achieving 15 Gb/s at 1.96 pJ/bit

Author:

Chang EricORCID,Narevsky Nathan,Han Jaeduk,Alon Elad

Funder

Defense Advanced Research Projects Agency

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper);2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

2. A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits: A High-Speed FFE SST Transmitter Example;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-05

3. CAD for Analog/Mixed‐Signal Integrated Circuits;Advances in Semiconductor Technologies;2022-09-30

4. Design and Automatic Generation of High-Speed Circuits for Wireline Communications;2019 International SoC Design Conference (ISOCC);2019-10-06

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