A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits: A High-Speed FFE SST Transmitter Example-Reference-Cited by-同舟云学术

A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits: A High-Speed FFE SST Transmitter Example

Published:2023-05 Issue:5 Volume:31 Page:622-635
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Kim Kwangmin¹^ORCID,Song Hyoseok¹^ORCID,Lee Byeongcheol²^ORCID,Kim Byungsub³^ORCID

Affiliation:

1. Department of Electrical Engineering, Pohang University of Science and Technology, Pohang, South Korea

2. Center for Next Generation Semiconductor Convergence and Open Sharing System, Pohang University of Science and Technology, Pohang, South Korea

3. Department of Electrical Engineering, the Department of Convergence IT Engineering, the Department of Semiconductor EngineeringGraduate School of Artificial Intelligence, Pohang University of Science and Technology, Pohang, South Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/10106533/10079925.pdf?arnumber=10079925

Reference22 articles.

1. Revisiting Routability-Driven Placement for Analog and Mixed-Signal Circuits

2. GUI-Enhanced Layout Generation of FFE SST TXs for Fast High-Speed Serial Link Design

3. On Closing the Gap Between Pre-Simulation and Post-Simulation Results in Nanometer Analog Layouts

4. Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design

5. Characterization of Equalized and Repeated Interconnects for NoC Applications

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1. Review: A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits;2023 20th International SoC Design Conference (ISOCC);2023-10-25