Design Tradeoffs in CXL-Based Memory Pools for Public Cloud Platforms

Author:

Berger Daniel S.1ORCID,Ernst Daniel1,Li Huaicheng2,Zardoshti Pantea1,Shah Monish1,Rajadnya Samir1,Lee Scott1,Hsu Lisa1,Agarwal Ishwar3,Hill Mark D.1,Bianchini Ricardo1

Affiliation:

1. Microsoft Azure, Redmond, WA, USA

2. Virginia Tech, Blacksburg, VA, USA

3. Intel Corporation, Santa Clara, CA, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference20 articles.

1. Memory connectivity platform for CXL 1.1 and 2.0,2022

2. Intel resource director technology (Intel RDT),2015

3. CXL use-cases driving the need for low latency performance retimers,2021

4. AMD unveils workload-tailored innovations and products at the accelerated data center premiere;su,2021

5. Network requirements for resource disaggregation;peter;Proc 2th USENIX Conf Operating Syst Des Implementation,0

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1. Pointers in Far Memory;Communications of the ACM;2023-11-17

2. Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

3. Aurelia: CXL Fabric with Tentacle;Proceedings of the 4th Workshop on Resource Disaggregation and Serverless;2023-10-23

4. Near to Far: An Evaluation of Disaggregated Memory for In-Memory Data Processing;Proceedings of the 1st Workshop on Disruptive Memory Systems;2023-10-23

5. Partial Failure Resilient Memory Management System for (CXL-based) Distributed Shared Memory;Proceedings of the 29th Symposium on Operating Systems Principles;2023-10-23

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