Exploring Performance and Cost Optimization with ASIC-Based CXL Memory

Author:

Tang Yupeng1ORCID,Zhou Ping2ORCID,Zhang Wenhui2ORCID,Hu Henry2ORCID,Yang Qirui2ORCID,Xiang Hao2ORCID,Liu Tongping2ORCID,Shan Jiaxin2ORCID,Huang Ruoyun2ORCID,Zhao Cheng2ORCID,Chen Cheng2ORCID,Zhang Hui2ORCID,Liu Fei2ORCID,Zhang Shuai2ORCID,Ding Xiaoning2ORCID,Chen Jianjun2ORCID

Affiliation:

1. Yale University and ByteDance

2. ByteDance

Publisher

ACM

Reference68 articles.

1. Dez Blanchfield. The cloud native convergence: A new era of data-intensive applications. https://elnion.com/2023/06/05/the-cloud-native-convergence-a-new-era-of-data-intensive- applications/.

2. FlatFlash

3. Shao-Peng Yang, Minjae Kim, Sanghyun Nam, Juhyung Park, Jin yong Choi, Eyee Hyun Nam, Eunji Lee, Sungjin Lee, and Bryan S. Kim. Overcoming the memory wall with CXL-Enabled SSDs. In 2023 USENIX Annual Technical Conference (USENIX ATC 23), pages 601--617, Boston, MA, July 2023. USENIX Association.

4. Compute Express Link (CXL). https://www.computeexpresslink.org/.

5. Huaicheng Li, Daniel S Berger, Stanko Novakovic, Lisa Hsu, Dan Ernst, Pantea Zardoshti, Monish Shah, Ishwar Agarwal, Mark Hill, Marcus Fontoura, et al. First-generation memory disaggregation for cloud platforms. arXiv preprint arXiv:2203.00241, 2022.

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