ML Processors Are Going Multi-Core: A performance dream or a scheduling nightmare?
Author:
Affiliation:
1. Electrical Engineering Department (ESAT), MICAS Laboratories, KU Leuven, Belgium
Funder
Flemish Government
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4563670/9950726/09950755.pdf?arnumber=9950755
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1. DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC
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4. 7.1 An 11.5TOPS/W 1024-MAC Butterfly Structure Dual-Core Sparsity-Aware Neural Processing Unit in 8nm Flagship Mobile SoC
5. mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator
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