Design of Low Power, High Speed, Low Offset and Area Efficient Dynamic-Latch Comparator for SAR-ADC-Reference-Cited by-同舟云学术

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Design of Low Power, High Speed, Low Offset and Area Efficient Dynamic-Latch Comparator for SAR-ADC

Published:2020-02 Issue: Volume: Page:
ISSN:
Container-title:2020 International Conference on Innovative Trends in Communication and Computer Engineering (ITCE)
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Author:

Bandla Kasi,A. Harikrishnan,Pal Dipankar

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9039701/9047749/09047792.pdf?arnumber=9047792

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Optimization of a Low-Power Comparator for a 10-Bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for General-Purpose Applications;2024 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE);2024-01-24

2. Design of Voltage Comparator with High Voltage to Time Gain for ADC Applications;Lecture Notes in Networks and Systems;2024

3. A 12Bits segment SAR ADC with low power switching method;2023 5th International Conference on Electronic Engineering and Informatics (EEI);2023-06-30

4. Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm;Chips;2023-02-27

5. A Novel Dynamic Latch Comparator Design and Analysis for ADCs;Intelligent Computing and Communication;2023

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