A Novel Dynamic Latch Comparator Design and Analysis for ADCs
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-1588-0_11
Reference16 articles.
1. Bandla K, Harikrishnan A, Pal D (2020) Design of low power, high speed, low offset and area efficient dynamic-latch comparator for SAR-ADC. In: 2020 international conference on innovative trends in communication and computer engineering (ITCE), Aswan, Egypt, pp 299–302. https://doi.org/10.1109/ITCE48509.2020.9047792
2. Goll B, Zimmermann H (1892) A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65. IEEE Trans Circuits Syst II Exp Briefs 56(11):810-814
3. Clerk Maxwell J (1892) A treatise on electricity and magnetism, 3rd ed., vol 2. Clarendon, Oxford, pp 68-73
4. Khosrov DS (2011) An improved low offset latch comparator for high-speed ADCs. Analog Integr Circuit Signal Process 66:205–212
5. Razavi B, Wooley BA (1992) Design techniques for high-speed, high-resolution comparators. IEEE J Solid-State Circuits 27(12):1916–1926
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