1. ReOVE: Restricted Out-of-Order Execution for Superscalar Processors with Vector Extension;Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design;2024-08-05
2. PUMICE: Processing-using-Memory Integration with a Scalar Pipeline for Symbiotic Execution;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09
3. Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications;ACM Transactions on Architecture and Code Optimization;2023-03
4. Minimalistic Vector Extension for Image Detection on Edge Nodes Using ‘VGG16’;2022 International Conference of Science and Information Technology in Smart Administration (ICSINTESA);2022-11-10
5. Adaptable Register File Organization for Vector Processors;2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2022-04