A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs-Reference-Cited by-同舟云学术

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A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs

Published:2001-07 Issue:7 Volume:36 Page:1120-1126
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Fujisawa H.,Takahashi T.,Nakamura M.,Kujigaya K.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/20201/00933470.pdf?arnumber=933470

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Ultra-Low-Voltage, Wide Signal Swing, and Clock-Scalable Dynamic Amplifier Using a Common-Mode Detection Technique;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2014

2. An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8:4 Multiplexed Data-Transfer Scheme;IEEE Journal of Solid-State Circuits;2007-01

3. 1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer;IEEE Journal of Solid-State Circuits;2005-04

4. 1-Gb/s/pin multi-gigabit DRAM design with low impedance hierarchical I/O architecture;2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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