An Ultra-Low-Voltage, Wide Signal Swing, and Clock-Scalable Dynamic Amplifier Using a Common-Mode Detection Technique-Reference-Cited by-同舟云学术

An Ultra-Low-Voltage, Wide Signal Swing, and Clock-Scalable Dynamic Amplifier Using a Common-Mode Detection Technique

Published:2014 Issue:12 Volume:E97.A Page:2400-2410
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

LIN James¹,MIYAHARA Masaya¹,MATSUZAWA Akira¹

Affiliation:

1. Department of Physical Electronics, Tokyo Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E97.A/12/E97.A_2400/_pdf

Reference30 articles.

1. [1] A. Matsuzawa, “Trends in high speed ADC design,” IEEE 7th Int. Conf. on ASIC (ASICON), pp.245-248, Oct. 2007.

2. [2] M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, “A low-noise self-calibrating dynamic comparator for high-speed ADCs,” Proc. IEEE Asian Solid-State Circuit Conf. (A-SSCC), pp.269-272, Nov. 2008.

3. [3] B. Razavi, Principles of data conversion system design, IEEE Press, New York, 1995.

4. [4] H. Fujisawa, T. Takahashi, M. Nakamura, and K. Kujigaya, “A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs,” IEEE J. Solid-State Circuits, vol.36, pp.1120-1126, July 2001.

5. [5] B. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq, and G. Van der Plas, “A 2.6mW 6 bit 2.2GS/s fully dynamic pipeline ADC in 40nm digital CMOS,” IEEE J. Solid-State Circuits, vol.45, pp.2080-2090, Oct. 2010.