Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/8945448/08933351.pdf?arnumber=8933351
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. All-nMOS Power-Rail ESD Clamp Circuit With Compact Area and Low Leakage;IEEE Transactions on Electron Devices;2024-09
2. A Novel Dual-Direction SCR Embedded With Segmental and Cross-Bridge Topology for High-Voltage ESD Protection;IEEE Transactions on Electron Devices;2023-08
3. Investigation of Different Conduction States on the Performance of NMOS-Based Power Clamp ESD Device;Journal of Electrical Engineering & Technology;2021-03-09
4. Using Schottky Barrier Diode to Improve Latch-Up Immunity for CMOS ICs Operating With Negative Voltage Sources;IEEE Electron Device Letters;2021-03
5. ESD Design and Analysis by Drain Electrode-Embedded Horizontal Schottky Elements for HV nLDMOSs;Electronics;2021-01-15
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