A Phase-Locked Loop Algorithm for Single-Phase Systems With Inherent Disturbance Rejection-Reference-Cited by-同舟云学术

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A Phase-Locked Loop Algorithm for Single-Phase Systems With Inherent Disturbance Rejection

Published:2019-12 Issue:12 Volume:66 Page:9260-9267
ISSN:0278-0046
Container-title:IEEE Transactions on Industrial Electronics
language:
Short-container-title:IEEE Trans. Ind. Electron.

Author:

Lima Francisco Kleber de A.^ORCID,Araujo Renato G.,Tofoli Fernando L.^ORCID,Branco Carlos Gustavo C.^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

http://xplorestaging.ieee.org/ielx7/41/8784422/08624567.pdf?arnumber=8624567

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An improved derivative‐based phase‐locked loop for single‐phase grid synchronization under abnormal grid conditions;International Journal of Circuit Theory and Applications;2024-08-07

2. Advanced Single-Phase PLL-Based Transfer Delay Operators: A Comprehensive Review and Optimal Loop Filter Design;Energies;2024-01-15

3. A Phase-Locked Loop With Inherent DC Offset Rejection for Single-Phase Applications;IEEE Transactions on Industrial Informatics;2023-01

4. A Nonlinear Loop Filter based PLL With Harmonic Filtering Capability for Single-Phase Grid Integrated System With Improved Dynamic Performance;IEEE Transactions on Power Delivery;2022-12

5. A Straightforward Quadrature Signal Generator for Single-Phase SOGI-PLL With Low Susceptibility to Grid Harmonics;IEEE Transactions on Industrial Electronics;2022-07

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