A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance-Reference-Cited by-同舟云学术

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A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

Published:2020-10-05 Issue: Volume: Page:
ISSN:
Container-title:2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC)
language:
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Author:

Simon William Andrew¹,Levisse Alexandre¹,Zapater Marina²,Atienza David¹

Affiliation:

1. Embedded Systems Laboratory (ESL), Swiss Federal Institute of Technology Lausanne (EPFL)

2. University of Applied Sciences Western Switzerland (HEIG-VD / HES-SO)

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9344049/9344068/09344087.pdf?arnumber=9344087

Reference26 articles.

1. 19.7 a16gb reram with 200mb/s write and 1gb/s read in 27nm technology;fackenthal;ISSCC,0

2. A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination

3. 13.3 a 7mb stt-mram in 22ffl finfet technology with 4ns read sensing time at 0.9v using write-verify-write scheme and offset-cancellation sensing technique;wei;ISSCC,0

4. STT-RAM based energy-efficiency hybrid cache for CMPs

5. A software approach for combating asymmetries of non-volatile memories

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