Dealing with Non-Idealities in Memristor Based Computation-In-Memory Designs
Author:
Affiliation:
1. Delft University of Technology,Computer Engineering Lab,Delft,The Netherlands
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9939277/9939284/09939618.pdf?arnumber=9939618
Reference45 articles.
1. Reducing the Impact of Phase-Change Memory Conductance Drift on the Inference of large-scale Hardware Neural Networks
2. Defects, Fault Modeling, and Test Development Framework for RRAMs
3. Parasitic Effect Analysis in Memristor-Array-Based Neuromorphic Systems
4. CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out
5. STT-RAM Cell Optimization Considering MTJ and CMOS Variations
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