1. A Case Study on Implementing Compressed DFT Architecture;2014 IEEE 23rd Asian Test Symposium;2014-11
2. Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms;20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07);2007
3. DFT infrastructure for broadside two-pattern test of core-based SOCs;IEEE Transactions on Computers;2006-04
4. Modular and rapid testing of SOCs with unwrapped logic blocks;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2005-11
5. Resource-constrained system-on-a-chip test: a survey;IEE Proceedings - Computers and Digital Techniques;2005