A High-Voltage LDMOS Compatible With High-Voltage Integrated Circuits on p-Type SOI Layer-Reference-Cited by-同舟云学术

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A High-Voltage LDMOS Compatible With High-Voltage Integrated Circuits on p-Type SOI Layer

Published:2009-10 Issue:10 Volume:30 Page:1093-1095
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Xiaorong Luo ,Tianfei Lei ,Yuangang Wang ,Huanmei Gao ,Jian Fang ,Ming Qiao ,Wei Zhang ,Hao Deng ,Bo Zhang ,Zhaoji Li ,Zhiqiang Xiao ,Zhengcai Chen ,Jing Xu

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/55/5263237/05235128.pdf?arnumber=5235128

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2. Stacked lateral double-diffused metal-oxide-semiconductor field effect transistor with enhanced depletion effect by surface substrate;Chinese Physics B;2019-03

3. Improving breakdown voltage and self-heating effect for SiC LDMOS with double L-shaped buried oxide layers;Superlattices and Microstructures;2017-02

4. A Novel 3-D Analytical Method for Curvature Effect-Induced Electric Field Crowding in SOI Lateral Power Device;IEEE Transactions on Electron Devices;2016-11

5. A 600 V High-Voltage IC Technique With a New Self-Shielding Structure for High Noise Tolerance and Die Shrink;IEEE Transactions on Electron Devices;2015-05

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