VLSI Implementation of an Improved Multiplier for FFT Computation in Biomedical Applications-Reference-Cited by-同舟云学术

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VLSI Implementation of an Improved Multiplier for FFT Computation in Biomedical Applications

Published:2015-07 Issue: Volume: Page:
ISSN:
Container-title:2015 IEEE Computer Society Annual Symposium on VLSI
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Author:

Ajay Arathi,Lourde R. Mary

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7307713/7308659/07309540.pdf?arnumber=7309540

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High Performance DIF-FFT Using Dissimilar Partitioned LUT Based Distributed Arithmetic;International Journal of Electronics and Telecommunications;2023-07-26

2. Booth-Encoded Karatsuba: A Novel Hardware-Efficient Multiplier;Advances in Electrical and Electronic Engineering;2021-10-03

3. Design and analysis of high performance and low power FFT for DSP datapath using Vedic Multipliers;International Journal of Electronics Letters;2021-04-11

4. VLSI Architecture for Combined R2B, R4B and R8B FFT using SDF and Modified CSLA;2021 International Conference on Computer Communication and Informatics (ICCCI);2021-01-27

5. A Radix-16 Booth Multiplier Based on Recoding Adder with Ultra High Power Efficiency and Reduced Complexity for Neuroimaging;Journal of Medical Imaging and Health Informatics;2020-04-01

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