SiLago-CoG: Coarse-Grained Grid-Based Design for Near Tape-Out Power Estimation Accuracy at High Level-Reference-Cited by-同舟云学术

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SiLago-CoG: Coarse-Grained Grid-Based Design for Near Tape-Out Power Estimation Accuracy at High Level

Published:2017-07 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
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Author:

Jafri Syed Mohammad Asad Hassan,Farahini Nasim,Hemani Ahmed

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7985547/7987474/07987490.pdf?arnumber=7987490

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Automating functional unit and register binding for synchoros CGRA platform;Design Automation for Embedded Systems;2024-06

2. Integer Linear Programming-Based Simultaneous Scheduling and Binding for SiLago Framework;IEEE Access;2024

3. Clock tree generation by abutment in synchoros VLSI design;Microprocessors and Microsystems;2023-10

4. Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures *;2023 26th Euromicro Conference on Digital System Design (DSD);2023-09-06

5. Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures;Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies;2023-06-14

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