Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM

Author:

He Zhezhi,Angizi Shaahin,Fan Deliang

Publisher

IEEE

Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. On-Device Continual Learning With STT-Assisted-SOT MRAM-Based In-Memory Computing;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08

2. A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-07

3. StreamPIM: Streaming Matrix Computation in Racetrack Memory;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02

4. Engineered Vertically Stacked NSFET Charge-Trapping Synapse for Neuromorphic Applications;ACS Applied Electronic Materials;2023-12-04

5. Self-Writing xnor Magnetic Random Access Memory for Binary Neural Network Acceleration;IEEE Transactions on Magnetics;2023-11

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